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SG1577 -- Dual Synchronous DC/DC Controller
April 2008
SG1577 Dual Synchronous DC/DC Controller
Features
Integrated Two Sets of MOSFET Drivers Two Independent PWM Controllers Constant Frequency Operation: Free-running Fixed Frequency Oscillator Programmable: 60kHz to 320kHz Wide Range Input Supply Voltage: 8~15V Programmable Output as Low as 0.7V Internal Error Amplifier Reference Voltage: 0.7V1.5% Two Soft-Start / EN Functions Programmable Over-Current Protection (OCP) 30V HIGH Voltage Pin for Bootstrap Voltage Output Over-Voltage Protection (OVP) SOP and DIP 20-pin
Description
The SG1577 is a high-efficiency, voltage-mode, dualchannel, synchronous DC/DC PWM controller for two independent outputs. The two channels are operated out of phase. The internal reference voltage is trimmed to 0.7V1.5%. It is connected to the error amplifier's positive terminal for voltage feedback regulation. The soft-start circuit ensures the output voltage can be gradually and smoothly increased from zero to its final regulated value. The soft-start pin can also be used for chip-enable function. When two soft-start pins are grounded, the chip is disabled and the total operation current can be reduced to under 0.55mA. The fixedfrequency is programmable from 60kHz to 320kHz. The Over-Current Protection (OCP) level can be programmed by an external current sense resistor. It has two integrated sets of internal MOSFET drivers. SG1577 is available in 20-pin SOP and DIP packages.
Applications
CPU and GPU Vcore Power Supply Power Supply Requiring Two Independent Outputs
Ordering Information
Part Number
SG1577SZ SG1577DZ
Operating Temperature Range
-40C to +85C -40C to +85C
Package
20-pin Small Outline Package (SOP) 20-pin Dual In-Line Package (DIP)
Packing Method
Tape & Reel Tube
All packages are lead free per JEDEC: J-STD-020B standard.
(c) 2007 Fairchild Semiconductor Corporation SG1577 * Rev. 1.0.1
www.fairchildsemi.com
SG1577 -- Dual Synchronous DC/DC Controller
Application Diagram
Figure 1.
Typical Application
Internal Block Diagram
Figure 2.
Functional Block Diagram
(c) 2007 Fairchild Semiconductor Corporation SG1577 * Rev. 1.0.1
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SG1577 -- Dual Synchronous DC/DC Controller
Pin Configuration
Figure 3. SOP-20 and DIP-20 Pin Configuration (Top View)
Pin Definitions
Name
RT
Pin #
1
Type
Description
Switching frequency programming pin. An external resistor connecting from this pin to GND can program the switching frequency. The switching Frequency Select frequency would be 60kHz when RT is open and become 320kHz when a 30k RT resistor is connected. Feedback Compensation Soft Start/Enable Over Current Protection Boost Supply High-Side Drive Switch Node Low-Side Drive Driver Ground Power Supply Low-Side Drive Switch Node High-Side Drive Boost Supply Over-Current Protection Soft-Start/Enable Compensation Feedback Control Ground Inverting input of the error amplifier. It is normally connected to the switching power supply output through a resistor divider. Output of the error amplifier and input to the PWM comparator. It is used for feedback loop compensation. A 10A internal current source charging an external capacitor for soft start. Pull down this pin and pin 17 can disable the chip. Over-current protection for high-side MOSFET. Connect a resistor from this pin to the high-side supply voltage to program the OCP level. Supply for high-side driver. Connect to the internal bootstrap circuit. Channel 1, high-side MOSFET gate driver pin. Switch-node connection to inductor. For channel 1 high-side driver's reference ground. Low-side MOSFET gate driver pin. Driver circuit GND supply. Connect to low-side MOSFET GND. Supply voltage input. Low-side MOSFET gate driver pin. Switch-node connection to inductor. For channel 2, high-side driver's reference ground. Channel 2 high-side MOSFET gate driver pin. Supply for high-side driver. Connect to the internal bootstrap circuit. Over-current protection for the high-side MOSFET. Connect a resistor from this pin to the high-side supply voltage to program the OCP level. A 10A internal current source charging an external capacitor for soft start. Pull down this pin and pin 4 can disable the chip. Output of the error amplifier and input to the PWM comparator. It is used for feedback-loop compensation. Inverting input of the error amplifier. It is normally connected to the switching power supply output through a resistor divider. Control circuit GND supply.
IN1 COMP1 SS1/ENB CLP1 BST1 DH1 CLN1 DL1 PGND VCC DL2 CLN2 DH2 BST2 CLP2 SS2/ENB COMP2 IN2 GND
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
(c) 2007 Fairchild Semiconductor Corporation SG1577 * Rev. 1.0.1
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SG1577 -- Dual Synchronous DC/DC Controller
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are given with respect to the network ground terminal. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.
Symbol
VCC BST1(or 2) CLN1(or 2) CLN1(or 2) GND DH1(or 2) CLN1(or 2) CLN1(or 2), DL1(or 2) PGND JA TJ TSTG ESD PGND to GND
Parameter
Supply voltage, VCC to GND BST1(2) to CLN1(2) CLN1(2) to GND for 100ns Transient
Min.
Max.
16 16
Unit
V V V V V V C/W C C kV V
-4
18 16
-0.3
VCC+0.3 1 90
Thermal Resistance, Junction-Air Operating Junction Temperature Storage Temperature Range Electrostatic Discharge Protection Level Human Body Model (HBM) Charged Device Model (CDM) -40 -65
+125 +150 2.5 750
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC TA Supply voltage
Parameter
Operating Ambient Temperature
Min.
+8 -40
Max.
+15 +85
Unit
V C
(c) 2007 Fairchild Semiconductor Corporation SG1577 * Rev. 1.0.1
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SG1577 -- Dual Synchronous DC/DC Controller
Electrical Characteristics
VCC=12V, TA =25C, unless otherwise noted.
Symbol
Oscillator fosc fosc,rt DON_MAX VREF AVOL BW PSRR ISOURCE ISINK VH COMP VL COMP Soft Start ISOURCE ISINK Protections IOSCET TOT TOT_HYS VOVP Output IDH RDH IDL RDL TDT ICC_OP ICC_SBY
Parameter
Conditions
RRT=OPEN RRT=GND 20kRRT
Min.
54 288 -10 85
Typ.
60 320 90 0.7000 77 3.5 50
Max.
66 352 10 95 0.7105
Unit
Oscillator Frequency Total Accuracy Maximum Duty Cycle Internal Reference Voltage Open-loop Voltage Gain Unity Gain Bandwidth Power Supply Rejection Ratio Output Source Current Output Sink Current Output Voltage Output Voltage Soft-start Charge Current Soft-start Discharge Current OC Sink Current Over-Temperature Over-Temperature Hysteresis Over-Voltage Protection of IN High-side Current Source High-side Sink Resistor Low-side Current Source Low-side Sink Resistor Dead Time
(1)
KHz % % V dB MHz dB
Error Amplifier VCC=8V,VCC=15V 0.6895
IN1=IN2=0.6V IN1=IN2=0.8V IN1=IN2=0.6V IN1=IN2=0.8V VCLPVCLN VCLPVCLN VCC=12V
60
80 500 5 100
100
A A V mV
8 0.8 90
10 1.0 120 150 20
12 1.2 150
A A A C C
VOVP/VIN VBST - VCLN=12V,VDH - VCLN=6V VBST - VCLN=12V VCC=12V,VDL =6V VCC=12V VCC=12V, DH & DL=1000pF VCC=12V, No load SS1/ENB=SS2/ENB=0V
112 1.0 1.0 10 3.3 1.7 3.3 1.7 3.1 40 4.3 0.55
125
% A
4.0 4 70 5.3 1.00
A ns mA mA
Total Operating Current Operating Supply Current Standby Current (Disabled)
Note: 1. When VDL falls less than 2V relative to VDH rising to 2V.
(c) 2007 Fairchild Semiconductor Corporation SG1577 * Rev. 1.0.1
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SG1577 -- Dual Synchronous DC/DC Controller
Typical Performance Characteristics
Unless otherwise noted, values are for VCC=12V, TA=+25C, and according to Figure 1.
Figure 4. V5p0 Power On with 1.6A Load
Figure 5. V3p3 Power On with 3A Load
Figure 6. V5p0 Power On with 15A Load
Figure 7. V3p3 Power On with 8A Load
Figure 8. V5p0 Power Off with 15A Load
Figure 9. V3p3 Power Off with 8A Load
(c) 2007 Fairchild Semiconductor Corporation SG1577 * Rev. 1.0.1
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SG1577 -- Dual Synchronous DC/DC Controller
Typical Performance Characteristics (Continued)
Unless otherwise noted, values are for VCC=12V, TA=+25C, and according to Figure 1.
Figure 10. 3p3 & V5p0 Phase Shift with Light Load
Figure 11. V3p3 & V5p0 Phase Shift with Heavy Load
Figure 12. Dead Time with Light Load (Rise Edge)
Figure 13. Dead Time with Light Load (Fall Edge)
Figure 14. Dead Time with Heavy Load (Rise Edge)
Figure 15. Dead Time with Heavy Load (Fall Edge)
(c) 2007 Fairchild Semiconductor Corporation SG1577 * Rev. 1.0.1
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SG1577 -- Dual Synchronous DC/DC Controller
Typical Performance Characteristics (Continued)
Unless otherwise noted, values are for VCC=12V, TA=+25C, and according to Figure 1.
Figure 16. Load Transient Response (Step-Up) 20k/22nF in Compensation Loop
Figure 17. Load Transient Response (Step-Down) 20k/22nF in Compensation Loop
Figure 18. Over-Current Protection (OCP)
Figure 19. Over-Current Protection (Hiccup Mode)
150 140 130 Iocset (uA) 120 110 100 90 -40 -25 -10 5 20 35 50 65 80 95 Temperature (oC)
Iocset 1 Iocset 2
Figure 20. Over-Voltage Protection (OVP)
(c) 2007 Fairchild Semiconductor Corporation SG1577 * Rev. 1.0.1
Figure 21. IOCSET vs. Temperature
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SG1577 -- Dual Synchronous DC/DC Controller
Functional Description
The SG1577 is a dual-channel voltage-mode PWM controller. It has two sets of synchronous MOSFET driving circuits. The two channels are running 180degrees out of phase. The following descriptions highlight the advantages of the SG1577 design.
Oscillator Operation
The SG1577 has a frequency-programmable oscillator. The oscillator is running at 60kHz when the RT pin is floating. The oscillator frequency can be adjusted from 60kHz up to 320kHz by an external resistor RRT between RT pin and the ground. The oscillator generates a sawtooth wave that has 90% rising duty. Sawtooth wave voltage threshold is from 1.2V to 2.8V. The frequency of oscillator can be programmed by the following equation:
fOSC, RT(kHz) = 60kHz + 8522 / RRT(k)
Soft Start
An internal start-up current (10A) flows out of SS/EN pin to charge an external capacitor. During the start-up sequence, SG1577 isn't enabled until the SS/ENB pin is higher than 1.2V. From 1.2V to (1.2 + 1.6 x DON / DON_MAX) V, PWM duty cycle gradually increases following SS/ENB pin voltage to bring output rising. After (1.2 + 1.6 x DON / DON_MAX) V, the soft-start period ends and SS/ENB pin continually goes up to 4.8V. When input power is abnormal, the external capacitor on SS pin is shorted to ground and the chip is disabled.
TSOFTSTART = CSS/ENB x 1.6 x DON / DON_MAX / ISOURCE (1)
(3)
Output Driver
The high-side gate drivers need an external bootstrapping circuit to provide the required boost voltage. The highest gate driver's output (15V is the allowed) on high-side and low-side MOSFETs forces external MOSFETs to have the lowest RDS(ON), which results in higher efficiency.
Over-Current Protection (OCP)
Over-current protection is implemented by sensing the voltage drop across the drain and the source of external high-side MOSFET. Over-current protection is triggered when the voltage drop on external high-side MOSFET's RDS(ON) is greater than the programmable current limit voltage threshold. 120A flowing through an external resistor between input voltage and the CLP pin sets the threshold of current limit voltage. When over-current condition is true, the system is protected against the cycle-by-cycle current limit. A counter counts a series of over-current peak values to eight cycles; the soft-start capacitor is discharged by a 1A current until the voltage on SS pin reaches 1.2V. During the discharge period, the high-side driver is turned off and the lowside driver is turned on. Once the voltage on SS/ENB pin is under 1.2V, the normal soft-start sequence is initiated and the 10A current charges the soft-start capacitor again.
IL(OCP)= [(RSENSE x IOCSET + VOFFSET) / RDS(ON) (VIN - VOUT) x VOUT / (fOSC x LOUT x VIN x 2) ] (2)
Over-Temperature Protection (OTP)
The device is over-temperature protected. When chip o temperature is over 150 C, the chip enters tri-state o (high-side driver is turned off). The hysteresis is 20 C.
Type II Compensation Design (for Output Capacitors with High ESR)
SG1577 is a voltage-mode controller; the control loop is a single voltage feedback path, including an error amplifier and PWM comparator, as shown in Figure 22. To achieve fast transient response and accurate output regulation, an adequate compensator design is necessary. A stable control loop has a 0dB gain crossing with -20dB/decade slope and a phase margin greater than 45.
where, VOFFSET (10mV) is the offset voltage contributed by the internal OCP comparator.
Error Amplifier
The IN1 and IN2 pins are connected to the corresponding internal error amplifier's inverting input and the outputs of the error amplifiers are connected to the corresponding COMP1 and COMP2 pins. The COMP1 and COMP2 pins are available for control-loop compensation externally. Non-inverting inputs are internally tied to a fixed 0.7V 1.5% reference voltage.
Figure 22. Closed Loop
(c) 2007 Fairchild Semiconductor Corporation SG1577 * Rev. 1.0.1
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SG1577 -- Dual Synchronous DC/DC Controller
1. Modulator Frequency Equations The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This transfer function is dominated by a DC gain and the output filter (LO and CO) with a double-pole frequency at fLC and a zero at FESR. The DC gain of the modulator is the input voltage (VIN) divided by the peak-to-peak oscillator voltage VRAMP(=1.6V). The first step is to calculate the complex conjugate poles contributed by the LC output filter. The output LC filter introduces a double pole, -40dB / decade gain slope above its corner resonant frequency, and a total phase lag of 180 degrees. The resonant frequency of the LC filter expressed as:
fP(LC) = 1 2 x L O x C O
fP1 = 0 fZ1 = fP2 1 2 x R 2 x C 2
(6)
1 = 2 x R 2 x (C1 // C2 )
Figure 24 shows the DC-DC converter gain vs. frequency. The compensation gain uses external impedance networks ZC and Zf to provide a stable, highbandwidth loop. High crossover frequency is desirable for fast transient response, but often jeopardizes the system stability. To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency. Place the zero at 75% of the LC filter resonant frequency. Crossover frequency should be higher than the ESR zero, but less than 1/5 of the switching frequency. The second pole should be placed at half the switching frequency.
(4)
The next step of compensation design is to calculate the ESR zero. The ESR zero is contributed by the ESR associated with the output capacitance. Note that this requires that the output capacitor should have enough ESR to satisfy stability requirements. The ESR zero of the output capacitor is expressed as:
fZ(ESR ) = 1 2 x CO x ESR
(5)
2. Compensation Frequency Equations The compensation network consists of the error amplifier and the impedance networks ZC and Zf, as Figure 23 shows.
Figure 24. Bode Plot
Figure 23. Compensation Loop
(c) 2007 Fairchild Semiconductor Corporation SG1577 * Rev. 1.0.1
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SG1577 -- Dual Synchronous DC/DC Controller
Layout Considerations
Layout is important in high-frequency switching converter design. If designed improperly, PCB can radiate excessive noise and contribute to converter instability. Place the PWM power stage components first. Mount all the power components and connections in the top layer with wide copper areas. The MOSFETs of buck, inductor, and output capacitor should be as close to each other as possible to reduce the radiation of EMI due to the high-frequency current loop. If the output capacitors are placed in parallel to reduce the ESR of capacitor, equal sharing ripple current should be considered. Place the input capacitor near the drain of high-side MOSFET. In multi-layer PCB, use one layer as power ground and have a separate control signal ground as the reference for all signals. To avoid the signal ground being affected by noise and have best load regulation, it should be connected to the ground terminal of output. Follow the below guidelines for best performance: 1 2 A two-layer printed circuit board is recommended. Use the bottom layer of the PCB as a ground plane and make all critical component ground connections through vias to this layer. Keep the metal running from the CLNx terminal to the output inductor short. Use copper-filled polygons on the top (and bottom, if two-layer PCB) circuit layers for the CLN node. The small-signal wiring traces from the DLx and DHx pins to the MOSFET gates should be kept short and wide enough to easily handle the several amps of drive current. The critical, small-signal components include any bypass capacitors (SMD-type of capacitors applied at VCC and SSx/ENB pins), feedback components 7 8 (resistor divider), and compensation components (between INx and COMPx pins). Position those components close to their pins with a local, clear GND connection or directly to the ground plane. Place the bootstrap capacitor near the BSTx and CLNx pins. The resistor on the RT pin should be near this pin and the GND return should be short and kept away from the noisy MOSFET's GND (which is short together with IC's PGND pin to GND plane on back side of PCB). Place the compensation components close to the INx and COMPx pins.
9
10 The feedback resistors for both regulators should be located as close as possible to the relevant INx pin with vias tied straight to the ground plane as required. 11 Minimize the length of the connections between the input capacitors, CIN, and the power switchers (MOSFETs) by placing them nearby. 12 Position both the ceramic and bulk input capacitors as close to the upper MOSFET drain as possible and make the GND returns (from the source of lower MOSFET to VIN capacitor GND) short. 13 Position the output inductor and output capacitors between the upper MOSFET and lower MOSFET and the load. 14 AGND should be on the clearer plane and kept away from the noisy MOSFET GND. 15 PGND should be short, together with MOSFET GND, then through vias to GND plane on the bottom of PCB.
3 4 5
6
(c) 2007 Fairchild Semiconductor Corporation SG1577 * Rev. 1.0.1
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SG1577 -- Dual Synchronous DC/DC Controller
Physical Dimensions
E
H
Detail A
1
b
10 e
F
c
A D
y
A2 A1
L Detail A
Figure 25. 20-Lead Small Outline Package (SOP)
Dimensions
Symbol Min. A A1 A2 b c D E e H L F y 0 10.007 0.406 12.598 7.391 2.362 0.101 2.260
Millimeter Typ. Max. 2.642 0.305 2.337 0.406 0.203 12.903 7.595 1.270 10.643 1.270 0.508X45 0.101 8 0 0.394 0.016 0.496 0.291 Min. 0.093 0.004 0.089
Inch Typ. Max. 0.104 0.012 0.092 0.016 0.008 0.508 0.299 0.050 0.419 0.050 0.020X45 0.004 8
(c) 2007 Fairchild Semiconductor Corporation SG1577 * Rev. 1.0.1
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SG1577 -- Dual Synchronous DC/DC Controller
Physical Dimensions (Continued)
D
20 11
E1
1 10
E
eB
A2 L b1 b e A1
A
Figure 26. 20-Lead Dual In-line Package (DIP)
Dimensions
Symbol Min. A A1 A2 b b1 D E E1 e L eB 2.921 8.509 0 6.223 24.892 0.381 3.175
Millimeter Typ. Max. 5.334 0.015 3.302 1.524 0.457 26.162 7.620 6.350 2.540 3.302 9.017 7 3.810 9.525 15 0.115 0.335 0 6.477 0.245 26.924 0.980 3.429 0.125 Min.
Inch Typ. Max. 0.210
0.130 0.060 0.018 1.030 0.300 0.250 0.100 0.130 0.355 7
0.135
1.060
0.255
0.150 0.375 15
(c) 2007 Fairchild Semiconductor Corporation SG1577 * Rev. 1.0.1
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SG1577 -- Dual Synchronous DC/DC Controller
(c) 2007 Fairchild Semiconductor Corporation SG1577 * Rev. 1.0.1
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